Research On The Error Detection Method Via Static Analysis Of RTL Designs

In recent years, with the rapid development of digital integrated circuit technology, the chip integration has been further improved, and the circuit scale has become increasingly large, and the complex degree is very higher. So the function accuracy of circuits is paid more and more attention. However, how to guarantee the accuracy of the digital integrated circuits is a question which has not been well resolved. In actual digital integrated circuit design processing, the design verification has became the key factor, and it is the largest time consumed processing, and its scale increases and efficiency increases behind the growth of the design dimension. Thus, how to implement all the verification processing automatically, and improve the efficiency of the design validation, making it able to complete the targeted design verification sufficiently, quickly and accurately is a question worthy to study.Existing design verification methods can be classified into two types: simulation-based method and formal method. Simulation-based verification method is with good scalability, but it is not complete and also usually quite inefficient to verify corner cases. The formal verification method is complete, but it is just applicable to designs of moderate size due to the "space explosion" problem. To find the potential common errors of integrated circuit designs, such as deadlocks in state machines, pin configuration errors, control signals valid value errors and so on, this paper introduces a novel error defection approach based on static analysis of register-transfer level designs. It could extract information from register-transfer level designs by static analysis technology, and check errors effectively and automatically. And it can help users to improve the quality of the hardware design and the efficiency of the design validation. The major contributions of this paper include:(1) An error defection method based on static analysis of register-transfer level designs is proposed.For detecting the potential common errors of integrated circuit designs quickly and efficiently, we introduce an effective error defection method based on static analysis of register-transfer level designs. First, we should store the standards of detecting error types in configuration files. Then, the method can scan register-transfer level design and extract the feature information based on static analysis technology. Last, it can finish the detection processing automatically through comparing the feature information with the standards of detecting error types. And the test procedure needs not the interaction and is the automation of code walkthrough method, and it only needs to modify the input of the design under verification and the design specifications, then the detection tool can be reused to detect errors in other register-transfer level designs. As this method is designed to detect most of the potential errors before design running and not to verification the design or the special functional requirements of design, it can serve as the preprocessing or adding method of the simulation-based validation method and formal validation method.(2) Based on the error defection method via static analysis of register-transfer level designs, we implement the static detection of three error types, such as deadlocks in state machines, pin configuration errors and control signals valid value errors.Based on the proposed method, we design the detection system and implement the static detection of deadlocks in state machines, pin configuration errors and control signals valid value errors. Also, we make the pointed experiment in a number of logic interfaces, and the proposed method can check errors effectively and automatically. Then we make a comparative experiment with simulation-based verification method and code walkthrough method, comparing with other methods, the proposed method is confirmed to improve the efficiency of the design validation effectively.