Research And Design Of Fully Digitally Controlled CMOS LC Oscillator

RF IC designers are facing more and more challenges in deep sub-micron CMOS process and SoC environment, scaling of voltage headroom and system integration make it extremely difficult to implement traditional RF circuits. Digital RF is a novel solution which is proposed to solve the above problems. Fully digitally controlled LC oscillator (DCO), which is presented recently, is the typical realization of digital RF. In this dissertation, the research and design of DCO is conducted and the principal contributions are as follows.In this dissertation, the non-ideal characteristics of traditional MOS varactors used in the DCO are analyzed, and an inversion-mode digitally controlled MOS varactor is proposed to alleviate the non-ideal characteristics. The phase noise of the DCO using inversion-mode varactors can be up to 9.5 dB lower than that of the DCO using traditional MOS varactors.In this dissertation, the nonlinearity of the MOS varactors caused by the large output signal of the DCO, as well as its influence on the performance of the DCO, is analyzed. A back-to-back in series digitally controlled MOS varactor is presented to avoid the nonlinearity of the varactors of the DCO. By using the back-to-back varactor structure, the phase noise of the DCO can be reduced by up to 8.1dB.In this dissertation, a method of co-simulating the digital Sigma-Delta Modulator (SDM) and the analog part of the DCO is presented. This method can be used to predict the spectrum and the phase noise of the DCO. As we know, it is difficult to predict the performance of the DCO in commonly used EDA tools due to the randomization effect of sigma-delta modulation in the DCO.In this dissertation, a low-spur pipelined MASH SDM is suggested to be applied in the DCO. Compared with traditional MASH SDM, the pipelined MASH SDM can reduce the power of the spurs by at least 25dB under the pipelined working conditions.In this dissertation, a single-stage 3rd-order multiple FeedForward (FF3) sigma-delta modulator is suggested to replace the MASH SDM applied in the DCO. Compared to pipelined MASH SDM, the FF3 SDM can reduce the phase noise of the DCO by 6dB while depressing the spurs by 20dB.In this dissertation, a novel complementary digitally controlled varactor pair is proposed. The complementary varactor pair can provide a much smaller effective switchable capacitance than the minimum size MOS varactor in the given process. Therefore, by using the varactor pair, up to 6 times finer frequency tuning resolution as well as lower quantization noise of the DCO can be achieved even in a large feather size CMOS process.In this dissertation, a high performance low power DCO for PHS transceiver is designed and realized. To improve the performance of the DCO, several circuit techniques such as inversion-mode digitally controlled MOS varactors, pipelined MASH SDM, dynamic element matching, digitally controlled MOS varactor matrix etc. are utilized. Measurement results demonstrate that the DCO can meet the specifications of PHS transceivers.Compared with the published DCOs in state of the art, this DCO features superior phase noise and power consumption. With the working SDM, the phase noise of the DCO at 100kHz offset frequency for 3.1GHz is below -102.3dBc/Hz while drawing 2.8mA of current from a 1.8V supply.The above contributions of this dissertation establish a certain basis for the design and research on the DCO based all digital phase locked loops and all digital single chip wireless tranceivers.