The Design And Research Of MVB Bus Administrator Based On FPGA

Along with the development of on-board data communication technology, as a special standard, Train Communication Network (TCN) is already used to be the on-board data communications international standard in recent years, which can be divided into two main component:the Wired Train Bus (WTB) and the Multifunction Vehicle Bus (MVB), and it is so widely used in rail transportation field whose interoperability and control real-time is demand higher, for instance, emu and subway trains etc. In TCN network, the MVB Class-4 device network interfaces which have the bus management function in MVB play a key role in the network. However, the core technology of the Train Communication Network is monopolized by some foreign companies. which leads to a huge resistance in the domestic popularization and application of the MVB technology. So there is a urgent need of the on-board data communication network of our country to research and develop the MVB Class-4 device network interface products with independent intellectual property rights.Based on analysis of the structure and function of the MVB agreement and the MVB Class-4 device network interface in depth, the MVB Bus Administrator is developed and researched based on the SOPC technology in this paper, which use FPGA as the hardware carrier, and the Verilog HDL language and C language as the development language.The MVB bus administrator which designed in this paper is divided in to two parts, the hardware and software, the hardware part of the system is divided into three modules,main control module, encode module and decode module.Firstly, encode module, decode module, encode and decode interface module are designed with Verilog HDL hardware description language, and used to realize the functions such as generation, receiving, testing, decoding, calibration, and storage of the MVB effective frame, then the encode and decode module are simulated, and the correct simulation results are showed in the paper; then a Nios II processor system which contains some components, such as NiosⅡCPU, TIMER, FLASH, encode interface and decode interface module, is constructed by the SOPC Builder tool, as the main control module, it is connected with the encode and the decode module in the top-level principle diagram, then the design of the hardware part of the system is completely. Secondly.The software's part of the bus administrator which include packet transmission, medium distribution, sovereignty transfer function, has been written and debugged in NiosⅡIDE, which is used to be the software development platform. Finally, the transmission of the process data packet of the whole system is practically tested, the result of the test shows that the MVB bus administrator designed in this paper can complete the function of process data packet transmission which accord with the MVB agreement.In addition, the problem of the bus collision is researched deeply and a more effective arbitration plan is suggested in this paper, which has laid a good foundation for further research.