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The MJPEG Video Codec System Based On SOCs

Posted on:2012-02-10Degree:MasterType:Thesis
Country:ChinaCandidate:P LiFull Text:PDF
GTID:2218330338962893Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
As information technology continues to evolve, the image information in the daily exchange of information among the people to play a wide range of applications. The current image processing system can be divided into two categories, general video image processing system and a dedicated image processing system. The former are generally based on general-purpose computer, such as workstations and computer and so on. The dedicated processing system in general is based on embedded system design, usually to DSP and programmable logic arrays to increase the system performance.This article first briefly describes the status of image compression and image compression history, I In various parts of the measure and compare, the proposed SOC image compression technology in the processing advantages and features, as well as JPEG encoding and decoding system, the function of each module. Then the application of SOC technology and MJPEG video codec system development platform for a brief introduction, and gives the IP core reuse based on the design. As a result of SOC technology team JPEG compressed, it can simultaneously decode multiple consecutive JPEG images. In this design, the paper further proposed a specific design MJPEG video image, and through the functional simulation and verification based on an integrated SOC feasibility of the program.On this subject in the JPEG codec IP core design and implementation of other, more complicated for the future and design of IP migration made a positive exploration, and through the design of the MJPEG based video codec SOC system solutions for the future through the realization of the SOC formats of multimedia video codec system provides a reference.
Keywords/Search Tags:MJPEG video codec, FPGA, Verilog HDL, IP core, SOC
PDF Full Text Request
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