Rf Receiver Front-end Design, Its Key Modules

The ever-increasing market and people's growing demand for wireless communications in recent years have given boost to research and development in relevant fields. Wireless transceivers are striving their ways towards high performance, high density yet with low power consumption and low cost. As one of the key blocks in RF transceiver, RF receiver Front-End comes into the research focus world widely. This thesis aims at the research and design of RF receiver Front-End targeting at the system and circuit design.In the first part of this thesis some of RF receiver's performance definitions and their specifications are described from the system viewpoint; after analysis and comparison have been done among three kinds of receiver architectures which are promising for single chip integration; and then design considerations are proposed after summarizing the characters of these three kinds of architectures. Two important parts of the RF receiver Front-End are discussed in detail in the next chapter:low-noise amplifier and mixer, in which process summarizations and comparisons are made about their topologies.The following sections of this thesis focus on the idiographic circuit design and measurement of the RF receiver Front-End and its key parts. And two prototype circuits are presented. One is a dual-band low noise amplifier (LNA) which can operate at mobile band of 2.1 GHz and WLAN band of 5.2GHz frequency is proposed. Input matching, noise matching and narrow-band amplifying are achieved at two frequency bands by adopting a switched inductive output load and a positive-negative feedback circuit. The proposed LNA is implemented in SMIC 0.13μm CMOS technology with a supply voltage of 1.2V. The LNA has gains of 20 dB and 14 dB and noise figures of 2.0 dB and 3.1 dB at 2.1 GHz and 5.2 GHz frequency bands, respectively, while dissipating power of 5.1 mW at the two frequency bands.The other is a RF CMOS zero-IF receiver front-end for dual-band (900MHz/1800MHz) GSM/EDGE applications is presented. The RF front-end comprises two separate LNAs and quadrature mixers. The current mode passive mixers are employed to lower the flicker noise. The RF front-end is manufactured in a 0.13μm CMOS process and occupies an active chip area of 0.9×1.0 mm2. The RF front-end achieves a NF of 2.9 dB and 3.2 dB, IIP3 of- 12.8 dBm and -11.9 dBm for the low band (900MHz) and the high band (1800MHz), respectively. The front-end consumes 16.3mA at 1.2V for the low band and 2 mA more for the high band.