Sgmii Subsystem. Soc System Authentication

With the rapid development of modern SOC (System on Chip), the size of the chip SOC is increasing larger and larger, and is becoming more and more complexly.in the SOC system development progress, SOC verification has been accounted for 70%-80% of the total workload. It already becomes one of the main bottlenecks of SOC system development. It is also one of the research interests in IC field.SGMII (Serial Gigabit Media Independent Interface) is a new high-speed serial interface used in Ethernet,. SGMII subsystem, which is based on MAC core modules, including CPPI (Communications Port Programming Interface) module, SGMII serial interface conversion module and Serdes module, supporting IEEE 802.3 protocol, is a Ethernet subsystem. It is a common IP in SOC system.The research in this article will use Verilog HDL language to build a system level verification environment and make a full validation of the SGMII subsystem function and related SOC system-level function. Modern SOC system will contain cores (CPU or DSP).All the test cases based on this verification environment are executed through the soft SOC core of RTL. Using the soft cores to control SGMII BFM, Only one C language test cases can be completed the behavior of software and hardware, and no need to control BFM directly using HDLs. There are two advantages doing so. Firstly, at compile aspect, it can save a lot of time at hardware compiling, after the first successful hardware compiled, all the software test cases need only software compiler and software implementation. Secondly, it could Improve SGMII BFM control efficiency. (Verification Integrated Property), This paper applied SGMII BFM is Synopsys company's VIP. With highly maturity, it can assure the DUT (design under Test) test quality. Because of its powerful function, it could finish all kinds of Ethernet behavior level simulation, it is very complex to use. And in this paper, it can greatly reduce to Ethernet VIP control workload using a well-designed AHB bus control system to encapsulate Ethernet VIP control method. Thirdly, simplify the design of test cases. Commonly, BFM is controlled by system-verilog or system-c. In this paper, Using software instead of hardware controls SGMII BFM, so SGMII BFM have a greatly increase in flexibility.In this paper, there is a complete validation process and grader testcase collecting method to make sure the testcases could cover the function points. Test cases planning first focus on SGMII subsystem IP in system-level integration between the channel and IP communications coordinated. Secondly focus on IP basic function, which based on the actual application scenarios.