Rom Code Automatically Generated Research

ROM information can only be read under normal circumstances and can not be changed. The information is generated under special conditions, even if out of power will not lose their stored information, it's non-volatile memory for storing fixed programs and data. It's character is high density and low cost. The information which is stored in ROM is the ROM Code. Existing solutions of ROM Code are diffusion layer and vias / contacts, for high density and low power applications, but its flexibility is relatively low. The method to generate contacts programmable ROM CODE is as below:1. Use C, TCL, PERL and other program languages to operate directly on the GDS, convert the text format code to the GDS format.2. Generate ROM GDS directly with code by ROM Compiler.GDS can be completed by both methods. But the defect is that these are not compatible with different technology, meanwhile can not confirm the code by schematic simulation. This thesis discusses how to generate ROM CODE layout and schematice automatically by PDK.PDK (Process design kit) for analog/mixed-signal IC circuit design techniques provides a complete set of files, that contains all the elements of a particular technology tool kit, which links IC design and IC manufacturing. Based on the Cadence full-custom IC design process PDK provides a complete solution, customers have a set of PDK to work on their integrated circuit design. It can generate powerful PCELL, and make circuit and layout closely, take advantage of these qualities as a starting point. We can develop a ROM PCELL with a process name argument. By selecting a different process value in PCELL, the ROM CELL under this process can be generated (including the symbol view and the Layout view), Finally throught the SKILL program to complete the automatic generation of schematic and layout so that it can be compatible with the generation of different techniques, different capacities, different bits wide, different rom structure with CODE. Generating the circuit and layout at the same time improves the speed of design and verification and ensures the correctness of flow. For FOUNDRY, such solution can not only unify procedure management under different technology and quick fully verification, but also if there is new process need to develop or the current process need update, there is no need to modify the main procedure. The only thing need to do is adjust the parameter of ROM PCELL to get the correct layout.