The Lzw-rs, The Fpga-based Data Compression Coding System Research And Design

The 21th century is a century of informationization, with the development of information technology, people's lives filled with data. The emergence of data compression technology, greatly improves the efficiency of data storage and transmission. The speed of traditionall methods of software compression are too slow.This paper designed a high-speed data compression system use hardware technology ,to meet the needs of some real-time compression.For data compression technic, people in pursuit of high compression ratio and compression speed all the while, make data occupied much small storage space, Obtain faster transfer speeds. This paper selected LZW compression algorithm as the research target, design a highly efficient data compression system. In order to make LZW compression algorithm with high compression efficiency and speed, this paper design using FPGA technology and take some improvements: 1. Take FIFO method to dictionary Update, Make dictionary with better compression efficiency. 2. Dictionary matching method was improved, Using multiple line data parallel match method to improve the speed. 3. Introduction a concept of virtual dictionary and designed parallel processing structure,the critical path of the data compression optimize used the processing pipeline technic. 4. Due to data transfer process, The channel noise will bring some error,.In this paper, design a RS fault-tolerant checkout module, to ensure the correct transmission of data, So that the whole system has some capacity to adapt. 5. The RS encoder and decoder module are designed together,use a E_d signal to control the encoding and decoding process, improve the rate of component reuse.When the system design completion, In this paper used popular EDA software Modelsim simulation and validate, experiments show that after compression and decompression can get the same results as the original. Take CYCLONEⅡseries EP2C35F672C6 chip as target carry through synthesis, results showed that the chip operating frequency is 47MHZ, data processing capacity achieve 201.42Mbps, the speed as much as other technology hardware compressor. The results show that the design can satisfy some real-time processing requirements, have some applications value.