Usb 3.0 Physical Layer Data Transmitter, The Research And Design

With the ever prevailing application of digital media and increasing volume, which sometimes exceeds 25 GB, of digital files being transferred, synchronized real time transmission has become an imperative feature of digital data transmission product nowadays. In 2007, Intel and other leading companies in the digital industry launched the USB 3.0 team to develop high speed USB transmission technology that is 10 times faster and more efficient than the current technology. This technology was co-developed by Intel, Hewlett-Packard (HP), NEC, NXP Semiconductors and Texas Instruments. It applies to synchronized real time transmission in personal computers, consumer electronics and mobile electronics. While the USB 3.0 is backward compatible, it is also easy to use and can be hot plugged as traditional USB technology. The goal of this technology is to deliver speed that is 10 times faster than the current technology based on the same structure as the current USB. Besides being more energy efficient by optimizing the specifications, USB 3.0 has connectors and cables that are backward compatible and supports fiber transmissions in the future.This article divides into two parts, which respectively focus on the Clock Generator and the Transmitter in the PHY micro cell of USB 3.0. These two circuits are also the most important technologies in the PHY micro cell. According to the specifications of USB 3.0, the clock generator should have the feature of Spread Spectrum Clocking, which in this article is implemented based on a combination of Phase Locked Loop andΣΔModulator. The article first discusses popular design methods on clock generators, among which there is the sigma-delta fractional-N phase locked loop that enables the Spread Spectrum Clocking. The article then discusses the system linear model and of the phase locked loop and the non-linearity and dead zone of the PFD/CP, the phase noise of the VCO, the noise shaping of theΣΔModulator and triangle wave generator. The article also describes the simulation results of each block and the whole circuit. The two structures of the high speed serializer are compared and analyzed. In order to balance the power consumption and the complexity of the layout, cascading of two structures is utilized to realize 5Gbps 40 to 1 serializer. The article finally researches and analyzes the structure of the line driver and the pre-emphasis. The simulation results are also analyzed. SMIC 90mm CMOS Mix Signal process is used to implement the design. The simulation results show that, the output frequency of the clock generator can reach 5GHz, and the high speed serializer and line driver can reach the same speed as well. The size of the whole chip is890μm×810μm.