Mobile Multimedia Broadcasting Frequency Domain Synchronization Key Technologies And Vlsi Implementation

With the development of wireless communication technology, mobile multimedia has been more and more widely used in people's life. Mobile TV, vehicular TV, and any other handheld device etc. are also becoming more and more popular. Thanks to the development of mobile multimedia, various TV and broadcasting programs can be watched anywhere and anytime, access to information becomes also more convenient and faster, which greatly enriches and facilitates people's life.In this paper, two typical mobile multimedia broadcasting standards, CMMB and DVB-H have been studied. A lot of research has been done on the synchronization algorithm in frequency domain in CMMB system, as well as algorithm improving. The transmitting-receiving platform for DVB-H has also been found, on which the performance of the classical algorithm has been validated. Through the comparison of the synchronization algorithm in frequency domain in these two standards, a set of multiplexing circuit structure for frequency domain synchronization has been established, which can be applied in both CMMB and DVB-H systems. FPGA testing result indicates that this structure can support the both two standards very well.The major work of this thesis includes:(1) Establishing the transmitting-receiving model for OFDM, as well as deeply researching the synchronization problems in OFDM system. The influence of carrier frequency offset, sampling frequency offset and symbol timing offset are quantitatively analyzed with mathematical model, which then indicates the importance of synchronization. Aiming at DVB-H and CMMB, which are two typical mobile multimedia broadcasting standards employ OFDM, the synchronization algorithm in frequency domain is deeply explored. Also, according to the similarity of frame structure and synchronization algorithm between the two standards, the hardware architecture design of two-standards-support frequency domain synchronization is completed.(2) To overcome the situation that the traditional estimation method of integer carrier frequency offset can't be used in CMMB system due to the scrambling of data in frequency domain, a new integer carrier frequency offset estimation algorithm based on the synchronization signal is proposed. The simulation result shows that this algorithm has good performance. The scrambling mode detection and descrambling algorithm based on the correlation of continual pilot is also proposed. At the same time, the classical residual carrier frequency offset and sampling offset tracking algorithm based on pilot correlation is applied in CMMB system. The simulation result shows a good performance, which meets the requirement of the system very well.(3) For DVB-H system, the classical algorithm of integer carrier frequency offset, residual carrier frequency offset and sampling frequency offset is employed. The reliability of the algorithm is sufficiently validated in 2K/4K/8K mode.(4) Based on the synchronization algorithm in frequency domain proposed in this article, and the similarity of frame structure and algorithm between CMMB and DVB-H, a hardware architecture of frequency domain synchronization which can support both the two standards is designed. Measures aiming at area and power consumption optimizing are also taken, such as taking part of the pilots into calculation in order to reduce complex multiplication times, coding the constants with CSD code in order to lower the hardware cost of constant multiplication, completing the iteration with the same register in order to lower the hardware and power consumption, simplifying the complex multiplication into sign bit calculation in descrambling, and so on. After the hardware design completing, functional simulation is taken with EDA tool, as well as design synthesis with Design complier. Compared with the hardware structure of frequency domain synchronization which supports single standard, the structure in this thesis realizes the supporting of two standards with only a little additional hardware cost. At last, FPGA platform is established, on which the function verification of this design is completed in the whole inner receiver environment.