| Recently, Battery-operated portable electronic devices such as cellular phones and other palm-size devices are in great demand in consumer electronic market. High performance power management ICs are mandatory in these devices for maximizing the system run time and extending operational life of the battery due to the slow development of battery technology. Furthermore, in order to decrease the size, weight and cost of these devices, miniaturization, low cost and high integration of the power modules are essential. In this paper, high efficiency, multi-modes, multiple-outputs power management Ics for portable electronic devices are researched and designed based on mix-signal CMOS process. The following works have been completed:The thesis begins with a brief review of the power converters Buck DC-DC working principle and introduce the use of high-frequency clock brought about by the advantages and the deterioration of conversion efficiency; through the power conversion circuit of the power loss analysis a number of efficiency improvement programs, as well as theoretical analysis of the efficiency of the best value and how the demand for power switch to select the appropriate size.And separately from the voltage control mode and current control mode (the average current-mode) two aspects of the system for accurate modeling, raised so that the stability of the system loop compensation program, and compared the voltage control mode and current control mode of the respective advantages and disadvantages.Then the design of each sub-circuit, realize the whole system and give the whole system performance indicators, through the whole simulation system functionality and performance.Finally, through the territory, an external device packages as well as studies to obtain a more comprehensive analysis of the power management chip.This thesis research and design of power management chips with voltage control mode and average current control mode of the dual-mode optional features; by increasing clock frequency (up to 12MHz), and thus can use a smaller inductor (0.47uH) and smaller capacitance (2.2uF), greatly reducing the system cost and size; and high clock frequency at the same time improve the accuracy of the conversion (the ripple is less than 5mV) with the speed; In addition, through analysis and precise loss of low-power design, at 100mA～500mA of load current range of the conversion efficiency of the entire chip would be able to maintain at about 90%. |
