This thesis introduces a method to analyses and to solve a kind of EEPROM failure.Through measure/compare,analysis,experiment and verification,I get a great deal of data to show the reason why the yield of wafer sorting is low,and find out the basic cause which make the EEPROM failure in chess mode check.The over etching of poly 1 results in gate oxide damage which makes the select transistor of EEPROM have a leakage.The leakage makes the select transistor keeps in "open" and loses its function.So,if the bit cell logic is "1",the cell is "open" and the bit line will have a significant leakage which results in the other bits in the same bit line are all "1" when they are selected for being read.In this case the EEPROM failure in chess mode is happened easily.Through modifying the chip design to increase the reference current of EEPROM, adjusting the etch process to increase the poly 1 CD and adding the RTP for gate oxide after polyl plasma etching to dispel the damage.We have solved the EEPROM checkerboard failure.The process validity has been verified on engineering wafer.The better process condition is fixed.The 1950's yield has been raised greatly.In this thesis,I find also a method to locate rapidly the EEPROM failure in chess mode check.At the same time,the design of the embedded EEPROM IP becomes perfect and the etch process is optimized.The solution of EEPROM benefits the series products.It is very importance and valuable to make the products cost down,to short the design cycle time,to optimize the etch process,in the feature. |