Encounter In The Cpf-based Low-power Embedded Soc Design

With the rapid growth of the wireless and portable electronic consumer markets, there is a constant demand for new technological advancements.This has resulted in more and more functionality being crammed into battery-operated products, increasing design and verification challenges for power management. Challenges like how to minimize leakage power dissipation,or how to design efficient packaging and cooling systems for power-hungry IC's,or how to verify functionality of power shut-off sequences early in the design,are expected to get even worse with the continuous shrinking of process nodes using today's CMOS technology.Managing design and verification for power will be as critical,if not more than,for timing and area in today's IC design flow for portable consumer electronics.Historically power optimization and implementation techniques have been leveraged at the physical implementation phase of the design.Certain advanced power management techniques like multiple power domains with power shut-off(PSO) methodology could only be implemented at the physical level(post synthesis). These advanced power management design techniques significantly change the design intent,yet none of the intended behavior could be captured in the RTL.This limitation had resulted in a big hole in the whole RTL to GDSII implementation and verification flow where the original RTL is no longer golden and cannot be used to verify the final netlist implementation containing the advanced power management techniques.The Common Power Format(CPF) is designed to address this limitation in the design automation tool flow by enabling the capture of the designer' s intent for advanced power management techniques.CPF provides support for all design and technology-related power constraints to be captured in a single file format for use throughout the RTL to GDSII design flow including verification,validation, synthesis,test,physical implementation,and signoff analysis. The automation enabled through CPF infrastructure support will be the answer to the growing power management design challenges faced by the industry.The introduction of CPF and its support will bring productivity gains and improved quality of silicon to designers without requiring any change to current legacy RTL.