Research On Low-Power Embedded Processor Design

In recent years, processors have gained very fast development. An obvious feature is, as process develops, the processors become more and more complex and performance is enhanced rapidly. At the same time, power consumption becomes a serious problem that the designers must face. Especially, as the mobile devices are popular, power consumption becomes a bottleneck of development of new generation processors. Thus, industry and colleges begin to pay more and more attention to low-power design.This thesis focuses on the microarchitecture design of processor, and try to open new research on low-power methods for future processors, power estimation methods at different design levels, microarchitecture design under power constrain, efficient ways to reduce power and area of critical units of processor, reducing leakage power under deep micrometer process, and embedded parallel multi-core design. Many creative methods are raised in this paper. The following is the main contributions of this thesis:1. To conduct low-power research at different design level, this thesis compares power estimation methods and analyzes related accuracy at different design levels.2. A complete study on branch prediction mechanisms uncovers the optimal scheme for embedded processor after tradeoff among area, power and performance. This work belongs to typical low-power research at microarchitecture level.3. A new low-power and less-area design method is raised for TLB, a critical part of memory management unit. This method can efficiently reduce power and area without expense of performance and timing delay.4. As process increases, leakage power becomes a very strict problem. The thesis deeply studies IVC (Input Vector Control) technology, and constructs...