All-digital Delay-locked Loop In The Fpga Design

FPGA has been developed more than two decades,and its logic gates increase from 1.2 thousands initial to millions and even more than 10 millions.Now, FPGA is widely used in many fiels,such as communication,cosumer electronics and auto electronics. However, there is no FPGA chips that made by ourself in domestic market. The FPGA chip is so important for IC design that we must have the FPGA chip with independent intellectual property rights. In order to achieve the advanced international level as soon as possible, we need learn and absorb successful and advaced experience, otherwise,it is difficult to have the silicon area optimaized and the best performance.As the increment of density and operation frequency of FPGA, the quality of clock in distribution network become more and more important. Clock skew and clock delay introduced by distribution network is harmfull for the system performance. Now both DLL and PLL can solve this problem, and for the output of DLL is stable and jitter free. So this paper choose DLL to eliminate the clock skew.DLL can implemented by analog technology which costs less silicon area and produces more prcise clock signal and digital technology which costs more silicon area but easily to design,low power dissipation, short lock time, and ability of resuse, this paper finally choose all digital DLL to design.The reserch subjects for designing all digital DLL in this paper is Vitex-E family PFGA.The author abstracted logic schematic from layout, sorted the circuits into different modules, analyzed and simulated all the modules in which spent more than one year .At last the author designed the all digital DLL successfully.This paper generally introduces the development of FPGA and its clock management technology, and analyzes the merit and disadvantage of DLL and PLL respectively. Then this paper illustrates the principle and design of every module and explains the operation of evry module by simulating the relative circuit. The EDA tools is Verilog-XL for all digital simulation , Spectre for all analog simulation, and HSIM for entire simulation.At last this paper provides output signal generator that can be uesed as duty cycle corrector and frequency synthesizer, which can provide required divided clock such as 1.5, 2, 2.5, 3, 4,5, 8, 16and multiple frequency clock signals.The all digital DLL provided by this paper implements in 0.18μm CMOS process in TSMC.The simulation result indicates the performance of designed DLL catchs the foreign similared products in aspects of the biggest jitter time that is 28ps and the highest power dissipation that is 200mW at 100MHz, working temperature range is -55℃~125℃, working frequency range is 25MHz~400MHz.