Research And Design Of 30～800MHz Frequency Synthesize Circuit Based On DDS

With the development of the frequency synthesis theory and the high speed Large Scale Integrated circuit, the requirements of the signal generator are improved in both military and civilian fields, then the high-speed Direct Digital Synthesis (DDS) is emerged. DDS has various advantages of high frequency conversion rate, high resolution of output frequency, small volume and programmable, etc. This issue makes fully utilization of these advantages of DDS, and uses PLL as the master clock of DDS, is significantly cost savings, also meets the requirements of clock of DDS. The frequency synthesis unit of Broadband Radio is realized on the whole. The project itself and the technology involved in it have some innovations and uniqueness.Firstly, the issue compares several types of frequency synthesis techniques, introduces the key technical indicators of DDS, puts forward the project of system hardware design, and demonstrates the parameters requirements of the subject. Then the specific circuit design and the implementation of the project and the problems in circuit debugging are mainly described. Finally, the testing results of the system are presented and an in-depth analysis of debugging and testing problems is given, then the practical solutions is promoted.