Multi-standard Programmable Io Ports In The Fpga Design

FPGA(Field Programmable Gate Array) is one type of programmable logic device. With the development of micro-electronics technology, designing and making integrate circuit can not only be charged with semiconductor manufacturers. System designers would more likely to design ASIC(Application Specific Integrated Circuit) chips themselves, and hope the designing period of the ASIC chips as shorter as possible. It should be best that designing appropriate ASIC chips in laboratory and diving into practical application immediately. Now, FPGA has been applied in communications, consumption elections and automobile elections comprehensively.IO Blocks is one of the most important modules in FPGA, its function is providing PAD connecting encapsulation and CLBs, receiving exterior signals, transmitting to interior of FPGA, exporting the result to extent circuit., and supporting different IO standards by configuration.FPGA allow users achieve different logic functions by their configuration. In IO Blocks, it can use different IO output/input buffer for different IO standards by configuration.This paper is about the designing and realization of the more standards configured Input/Output Block, and expand a module for competing two-port IO standards on the base of ordinary only single-ended standards support IO circuit. For example,compare with single-ended standards, one of the two-port IO standards LVDS has more advantage.(1)Smaller transmit signal swing range, lower power consume, current on different wires are lower than 4mA,output impedance is about 100ohm,and suitable for parallel transmission.(2)It can work on low voltage as 2.5V VC CO.(3)LVDS allow input voltage change from 0V to 2.4V,voltage swing rang is 400mV,it allow input common voltage change from 0.2V to 2.2V,and allow 1V rang between receive port and send port.This paper use 0.18μm 1.8V/3.3V mix-techniques, assistant with Xilinx FPGA exploitation tool ISE, having designed a IO module, which now use in Virtex-FPGA-family produced by Xilinx, having agile programmable ability and fineness adapt ability. It can support more than 20 IO standards, including signal-ended standards and two-port IO standards(for ex LVDS).Its selected IO resources include: choice of IO standards, configuration control of output drive ability, choice of swing ability, input delay and so on. In this design, more than 20 standards(including LVDS) achieve anticipate standard according to the described of user-handbook.