Design And Implementation Of Packet Input And Output Processing Module For TTE-ET Service

In recent years,with the new requirements of network applications for network technology,network technology has been fully developed.This is not only reflected in the demand for standard Ethernet access,but also in some emerging application scenarios or some that require to be upgraded.As an indispensable relay station in the network topology,the switch directly affects the development of network form.Functionally,we often hope that the switch can handle network data of different levels and different attributes,making the switch easier to network and standardize,and adapting to different network environments.In terms of performance,we want switches to have more access ports and higher port rates to accommodate the ever-evolving network topology and diverse terminal devices.Since the rise of the network concept,with the continuous iteration of switch technology,from the switching mode to the switch architecture,the switch has been following the development of the times,and derived a variety of switches that support specific applications and specific needs from the standard Ethernet switch.However,with the diversity of user access data and the difference in requirements,more application scenarios urgently need a switch that can simultaneously support multiple different levels of service forwarding.Time-triggered Ethernet(TTE)switches are a new generation of switches that are highly reliable,redundant,time-determined and support multiple different communication services,and have important applications in aerospace,rail transit,Internet of Things,etc.In this paper,combined with the project undertaken by the laboratory,“Time-triggered Ethernet Switch Module R&D”,based on the design concept of dual-plane,the eventtriggered(ET)switching plane packet input/output processing module is designed and implemented.Firstly,it introduces the background and development status of TTE switches.On this basis,for the ET service,the switch network with Crossbar as the switch architecture is designed to accomplish data switch.Secondly,in the case of multi-port aggregation,the design implements packet input processing,including service differentiation,data processing,table looking up,and capture&insertion.Then,for the Crossbar switching architecture,the output scheduling of the packet and the biplane output arbitration are designed.Finally,the software performs the simulation analysis of the above functions,and implements the board-level test verification based on the Field-Programmable Gate Array (FPGA)platform.The core working points of this paper include: firstly,based on the dual-plane switching network architecture,with the Crossbar switching network as the event-triggered service switching structure,it designed and implemented the packet input and output processing of the event-triggered service;secondly,because the switch needs to be connected with the upper-layer CPU Interacting,so the design implements a multi-channel capture&singlechannel insertion interaction process,and at the same time implements the configuration function for the internal switching table and registers of the switch;thirdly,because the whole switch is a dual-plane design structure,at the output interface,an output arbitration mechanism is designed to arbitrate the output of synchronous frames,time-triggered services and event-triggered services,and make sure that the output interface is used reliably and efficiently.