Used Hdmi Transmitter, Charge Pump Phase-locked Loop And Design

With the development of terminal display technique on high definition large-screen,the high-definition multimedia interface(HDMI) criterion appears.After six years' development,its application is more and more wide.According to this background,a clock frequency multiplier circuit,used for HDMI source chip,is designed in this thesis and satisfies the newest HDMI criterion. The circuit can generate an output clock with a frequency five times of its input clock in the range of 25MHz to 340MHz so as to be used to serialize the parallel input data. In this thesis,specific tasks are carried out,focusing on the design and implementation of a high-speed low-jitter CP-PLL(Charge-Pump Phase-Locked Loops).In the first part,the PLLs(Phase-Locked Loops) is analyzed and researched on the system level.At first,a continuous-time linear model and a discrete-time model is introduced so as to derive the conclusions for loop parameters design,which pave the way for system level design and optimization of high-speed low-jitter CP-PLLs. Second,after the introduction of these two models,a new discrete-time model is put forward,which reveals the relationship between the continuous-time and discrete-time. Third,PLLs' phase noise is analyzed and the key element of CP-PLLs,namely, voltage controlled oscillator is further studied with hajimiri's model which provides theoretical basis for improving the noise performance of CP-PLLs.The part of CP-PLLs' circuit design is aimed at the specifications on high speed and low jitter.According to the theory summarized in the analysis on the system level, the design flow is given based on system level,behavioral level and circuit level.The circuits structure,especially the improvement parts are explained in detail.The Charge-Pump Phase-Locked Loop(CP-PLL) is fabricated in TSMC 0.18μm 1P6M 1.8V/3.3V mixed-signal CMOS technology.The simulation of the whole circuit shows that the circuit can satisfy the requirement for the clock frequency multiplier circuit in HDMI-source chip.