.0.35 ¦¬m Enhanced 13.5v High-pressure Technology Platform Research And Development And Optimization,

With the rapid development of very-large-scale-integrated-circuits (VLSI),its integrity density is increasing and new requirements are demanded for designing and process.This thesis describe that Company established new enhanced 13.5 V HV process at 0.35μm platform together with worldwide famous design house in order to maintain its own advantages in the highly competitive semiconductor marketing.A large number of process modules have been optimizated during development.One of the most important module improvement is the combination of new LOCOS process development with poly gate lithography process.In LOCOS dry etching,silicon loss maintained at about 100 - 200 A,pad oxide layer reduced from 300 A to 135 A,and LOCOS oxide thickness change from 5000 A to 4000 A.Then the bird's beak can be effectively controlled below 0.1μm level,which breaks though the company's original technology bottle neck and achieves 0.4μm width devices.At the same time low-voltage device width is also reducd,which is a key to shrink the entire chip area.Employing BARC in poly gate lithography process could narrow pattern difference within single chip and the stability of process can be improved to provide a sufficient margin of production with little cost.We also solved problems of WSi_x peel and contact etch arcing to increase product yield,make a contribution for successful mass production.Final fixed HV device performance meet the requested of customer with Idsat of HVNMOS is about 600μA/μm and HVPMOS is around 400μA/μm.Through the reliability test the devices' lifetime can be guaranteed for more than 10 years.