Research And Design Of LDPC Decoding Algorithm In The Multi-Standard DTV

This paper is originated from the project named the multi-standard digital television (DTV) demodulation solution for DVB-S2/C2/T2and DTMB in Shanghai Bwave Technology Co., Ltd.. Compared with the single-standard DTV demodulation solution, the multi-standard DTV demodulation solution has the advantages of low cost, high integration and convenient maintenance and management, and has become the preferred solution for the future DTV demodulation. However, the research on the multi-standard DTV demodulation solutions is not deep enough, and a lot of the fusion schemes for various DTV transmission standards are studied, such as the fusion scheme for a new generation DTV transmission standards DVB-S2/C2/T2and DTMB standard which was included in the international standard list shortly before. Following the development trend of the multi-standard DTV demodulation solution, this paper has researched on the decoding algorithm of LDPC codes in the multi-standard DTV demodulation solution for DVB-S2/C2/T2and DTMB, and put forward the solution of the LDPC decoding algorithm, and designed of the iteration number and the fixed-point quantization scheme of LDPC decoding in the practical application, so as to lay a solid theoretical foundation for the FPGA hardware implementation of the LDPC decoder in the multi-standard DTV demodulation solution.This paper firstly studies on the decoding algorithm of LDPC codes in the multi-standard DTV demodulation solution for DVB-S2/C2/T2and DTMB, and put forward that the preferred LDPC decoding algorithm in the practical application is Offset Min-Sum algorithm based on layered message passing mechanism by simulating and analyzing. The simulation results demonstrate that this solution not only has lower decoding complexity, but also has better decoding performance.In order to the practical application of the multi-standard DTV demodulation solution for DVB-S2/C2/T2and DTMB, this paper secondly designs of the iteration number and the fixed-point quantization scheme of LDPC decoding. By simulating and analyzing the decoding performance of LDPC codes under different iteration numbers and different fixed-point quantization schemes, and considering the compromise of the hardware implementation cost and the decoding performance, this paper presents that the preferred LDPC decoding iteration number is30-40times in the practical application. And the preferred LDPC decoding fixed-point quantization scheme is the combination of entrance fixed-point scheme (5,1,1) and interior fixed-point scheme (8,1,3) in the practical application, and the simulation results show that the fixed-point quantization performance loss is within0.1dB under this scheme. The paper also concludes that the dynamic range in the entrance fixed-point scheme and the accuracy in the internal fixed-point scheme have a large influence on the decoding performance of LDPC codes in this multi-standard DTV demodulation solution.For the entrance fixed-point quantization of LDPC decoding, this paper presents a dynamic adjustment accuracy scheme, and the simulation results demonstrate that the decoding performance of LDPC codes is very close to or even more than floating-point performance when only quantizing the entrance of the LDPC decoder. Compared with the fixed-point quantization schemes which are used usually now, this scheme not only reduces the complexity of the hardware implementation, but also improves the performance loss resulted by the entrance fixed-point quantization, so as to enhance the fixed-point performance of the whole algorithm.This paper has theoretically solved the problems relating to the decoding of LDPC codes in the multi-standard DTV demodulation solution for the DVB-S2/C2/T2and DTMB, so as to lay a solid theoretical foundation for the FPGA hardware implementation of the LDPC decoder in this multi-standard DTV demodulation solution.