High Performance Bjt. Nanometer Cmos Process Research And Modeling

With the scaling of CMOS technology on silicon, process feature size becomes smaller and smaller, up to now, 32nm technology on 12-inch wafer has become the next technological target. CMOS technology on Silicon is widely used in digital circuit, mix-signal circuit, and RF circuits because of it's obvious advantages like high performance, high integration, low power, and low cost. However, despite of these advantages, it is not without it's limitations, the low frequency 1/f noise is one of them, which could reduce the performance of RF circuit like mixer.Bipolar transistors can provide speed, current driving capability, and low-noise performance, By combining both technologies on the same chip, the performance of the circuit can be greatly improved. Most existing BiCMOS processes combine high performance bipolar transistors with MOSFETs this results in a rather complex and expensive process due to the technological incompatibility of the two types of transistors. A more economical solution would be to use the parasitic bipolar transistors, which are inherently available in CMOS process. In this paper, advanced lateral and vertical bipolar transistors have been designed and fabricated by SMIC 130nm and 90nm RF CMOS process. The performance of those novel bipolar transistors have been improved through the optimization of device structure and fabrication process, the base width of the designed lateral bipolar transistor can be reduced to the level of 100nm especially in 90nm RFCMOS process. Those advanced bipolar transistors can be used in circuit applications to improve the performance and lower the cost, and they can also be very helpful in the design of RF ESD protection circuit.The main work included in this paper:(1) Design of novel lateral and vertical bipolar transistor, novel lateral and vertical CMOS bipolar transistor have been designed and fabricated by the SMIC 130nm and 90nm RF CMOS process.(2) Test and characterization of the designed novel bipolar transistors, I-V performance of the bipolar transistors on different conditions has been characterized. The effects of transistor structure, base doping concentration, base width (feature size), the shape and area of emitter on the common emitter current gain have been studied.(3) Modeling of the proposed novel CMOS bipolar transistors, SPICE model has been developed based on the experimental results, the developed SPICE model is based on Gummel-Poon model and the simulation results can fit the experiment very well.