Dvb-t Receiver Ip Core Implementation And Verification,

At present, The world-wide digital television standards include the DVB-T that developed by Europe,and the ATSC by America,the ISDB-T by Japan and the DMB-T that published by China on May 2006。The Digital Television Broadcast have many particular fineness To contrast with analog TV, it is widely popularized in the world since it appeared。The DVB-T digital terrestrial broadcast system standard is the earliest being put forward by the ETSI(Europe Telecommunication Standard lnstitue)and adopting at large by the countries of Europe and beyond of Europe, it has a wide influence on the communication field。Usually ,the DVB-T receiver is mainly composed of the iterpolator module,FFT module,synchronization module,channel estimation and correction module,constellation demapper module,inner De-interleaving module,Viterbi Decoder module,uter De-interleaving module,RS Deoder module etc, due to the complexity of wireless channel transmition and the requirement for high SNR, the arithmetic of the synchronization and channel estimation in the whole system are very important。This paper give a generic introduce for the synchronization arithmetic, but stress on a new arithmetic of the channel estimation and correction that have been implemented successfully in our DVB-T design, also the paper will give a further performance contrast and analysis relative to the other different channel estimation arithmetic in the different channel conditions.In the course of the verification,we use the VCS tool for software simulation, also we use a FPGA hardware platform to do the real-time prototype verification, but this real-time verification system requires the prototype system must achieve the speed that the real chip can run, the gates count for this IP is about 300K,so some of advanced FPGA design technique will be applied, this paper also will give a summary of FPGA advanced synthesis and implement skill.DVB-T is as a part of DFE(Digital Front End) have been integrated into a multimedia chip, the whole chip was manufactured by the TSMC 65nm CMOS technology.a abundance of tests have been done on the module,include the fuctions test, high-low voltage test, wearing test and the high-low temperature test etc, the result justfy the module achieves the design frequency and also the fuctions playing are well,it is completely met the design requrements.The author was mainly finish the following jobs in the project:read OFDM and DVB-T relative documents, understand the design theory of the whole system, compare above three sorts of the channel estimation and correction arithmetic,and use the optimum scheme and models it with systemc language and done much simulation works for it. lastly, simulate the whole design and verify it on FPGA platform,and analysis the data results.