Simulation And FPGA Implementation Of Synchronization In Digital Television Terrestrial Broadcasting Transmission System

Chinese Digital Television Terrestrial Broadcasting (DTMB) transmission standards was formally tabled on August 30,2006. The problem of how to design a steady receiver adapts to the standard is still the basic technical difficulty and research focus of the DTMB system. Study and implementation for DTMB system is of tremendous practical value and broad market prospects.The FPGA-based hardware implementation and design of the receiver's digital head system of Chinese DTMB system has been completed in this dissertation, including the realizations of the Hilbert filter, digital downconverter (DDC) and all the synchronization system. Firstly, the developing status of digital television terrestrial broadcasting, which is followed by the whole structure introduction of the transmitter and system summary of the receiver of Chinese DTMB is introduced. Then, the design of baseband converter, which is composed of Hilbert filter and digital downconverter, is introduced importantly in chapter 3. This dissertation has bringed up a pipelining transposed structure for implementing the Hilbert filter. By utilizing CSD representations of filter coefficients to replace the multiplier with shift adder and optimal Reduced Adder Graph (RAG) algorithm to share the tap coefficients to reduce the resource cost. Implement the DDC with CORDIC algorithm, which reduce the FPGA resource cost with its iterative shift operation, and also avoiding the disadvantage of traditional DDC method in variable phase situation.In chapter 4, the arithmetic analysis and architecture design of the synchronization system of the receiver are introduced in detail. The timing domain synchronization including symbol, sampling and frequency synchronization is proposed according to the characteristics of frame structure of DTMB system. Symbol and sampling synchronization is based on the PN sequence correlation. Recovery the optimal sampling signal by tracing the timing drift by a closed-loop controlled interpolator filter, which is adjusted by timing error. Bring up a frequency offset correction method using closed-loop controlled structure, and deal with frequency offset estimation and compensation by utilizing CORDIC algorithm. It firstly compensate large scale frequency offset by frequency scan, then estimate the frequency offset by using the correlation of PN and its delay in time domain. Adjusting the estimation range and estimation accuracy by changing the delay time to trace the frequency offset. At the same time, this dissertation has raised the process of the phase matching in the mode of changed PN. Simulation and FPGA verification is fulfilled in the final.