The Second Generation Of European Digital Terrestrial Television Broadcasting Standard In The Channel Estimation And Its Vlsi Structure Research

DVB-T2is the most brand new digital television broadcasting standard so far, consisting of the most advanced digital television broadcasting technology in the world. It is of great importance to make certain research on it for the development of digital television technology of our nation and for the developing of our self-patent digital television standard.This thesis mainly concentrates on the channel estimation and equalization the key technology of DVB-T2. There are eight pilot patterns proposed in DVB-T2, and three of them are adopted here to find the most suitable interpolation method for channel estimation. And the corresponding VLSI implementation technology is also discussed here to gain a best balance between performance, area and power to implement this method. The thesis consists of the following.1, Briefly introduced the development of digital television broadcasting technology both home and abroad. Discussed the issues faced by nowadays digital television broadcasting technology, including the higher spectrum efficiency required by the reduced spectrum resources, ever-growing demands for more function and more flexibility.etc. Briefly introduced the basic principle of OFDM and wireless channel model proposed in DVB-T2.2, Three of the eight pilot patterns proposed in DVB-T2are chosen to find the most suitable method for channel estimation. Comparison has been made on the influence of number of Taps for the interpolation and the behavior of the interpolation in different channel model. Comparison also made on the chosen Lagrange interpolation and bilinear interpolation with the same tap number. An optimal arithmetic has been chosen based on the balance between precision and complexity. Point fixing are made at last to preview the performance of its hardware version.3, VLSI implementation is made for the established interpolation arithmetic, including the overall architecture design, module function schedule and its performance optimization. Certain optimizations are made to reduce the complexity and computation. Mainly the division change into multiplication of reciprocal or look up table. What’s more, a release and lock mechanism is devised to control the write and read RAM group.