Based On The Design And Realization Of New ¦² ¡÷ Class-d Amplifier

With the development of the computer and communication technique, the value of the class D audio amplifier becomes important. Class D audio amplifier technology is widely used in many places including flat-display, PDA, mobile phone, and so on.With the requirement of the product performance, the requirement of the class D audio amplifier is become higher.The class D audio amplifier is based on sigma-delta modulation and over-sampling signal process. Digital-to-analog converter based on sigma-delta modulation, over-sampling filter, analog H bridge drive and analog low-pass filter are the main difficulties of the design. DAC sigma-delta modulator and over-sampling filter implemented by digital circuit could make full use of virtues of modern VLSI technologies such as high speed, high circuit density and low cost.This paper will focus on designing and implementing digital circuit of class D audio amplifier --- DAC sigma-delta modulator, both the SNR and the RPF should be controlled to get a high performanceas in this design.In order to achieve higher SNR but lower RPF with less place area, we choose the 1bit single-loop sigma-delta modulator. We could use ChebyshevⅡhigh filter's function to gain the system parameters, and optimize the locations of zeros and poles for DAC sigma-delta modulator, which both are stable modulators and the input signal of the modulators can achieve maximum.Over sampling filter is made up of Interpolator filter and CIC filter. Implement of multi-level filter could save the quantity of calculate and storage for FIR. Multi-phase architecture of filter is used in interpolator. Because timing is easy to satisfy, how to save areas is taken as the first considered factor. Through multi-level filter, left and right channel sharing combinational logic module and using TDMA in the sequential process of filters, the circuit area could be reduced observably.In order to satisfy most customers' requirement, the design support the sample rates of 44.1k, 48k and those refer to these two. There are 6 sample rates; the data-width can be chosen from 16bits to 24bits; there are 4 modes for digital audio interface. After the flow of system design, rtl coding, DFT design, FPAG verification, DC synthesis, place and route, STA, and timing verification, the digital layout is shown in the end. This chip has been implemented in the SMIC 0.18μm CMOS process. Test result shows that the chip has achieved the design target.