A Class-D Audio Amplifier Design Based On FPGA

With the rapid growth of electronic products digitally and portability,a new generation of audio equipment has more and more requirements for power consumption.Compared with the traditional linear power amplifier,Class D power amplifier has high power efficiency,thus it is widely used in high-power audio equipment and portable devices.With the development of digital signal processing technology,conventional analog Class D power amplifiers require the addition of digital-to-analog converters(DAC)to handle digital signals,and this will increased signal noise and distortion.In contrast,digital Class D power amplifiers have lower power consumption and chip area,and can be directly compatible with digital audio systems.So,digital Class D amplifier has become the focus of the current research.This paper is dedicated to the design and implementation of pulse width modulation(PWM)algorithm in digital D class power amplifier.Firstly,the existing modulation algorithm of digital D class power amplifier is studied and analyzed.And then,a new sampling algorithm of dC-LAG-NR which can effectively reduce the modulation harmonic distortion is proposed.Then,The system-level simulation of Class D audio power amplifier based dC-LAG-NR algorithm is established to verify the feasibility of the algorithm.Then,the hardware circuit based on dC-LAG-NR sampling algorithm is accomplished by FPGA.The power amplifier circuit and filter circuit are simulated by Orcad software,and then PCB board circuit design is completed.Finally,a test platform of digital D class power amplifier circuit is built for analysis,and optimization.The test result shows that when the input signal frequency in range of 0~20k Hz,the harmonic distortion correction effect based on dC-LAG-NR sampling algorithm is better than other algorithms.Simulation results based on Orcad software show that the power amplifier's total harmonic distortion(THD)is under 1%,power efficiency is up to 98.46% that meet the power efficiency requirements.Due to the lack of precision of the digital signal and the nonideal effect of the power output stage,the PCB board test shows that the circuit performance is deteriorated and the total harmonic distortion(THD)is about 20%,and the power efficiency is about 80% in the low power range.Combined with the circuit simulation and the measured results,the sampling algorithm of dC-LAG-NR proposed in this paper canoptimize the harmonic distortion of the class D power amplifier circuit.