Intermediate Frequency Channel Of The Digital Receiver Program And Algorithm Research,

The analog to digital conversion (ADC) is realized at the antenna in ideal software radio (SR), which demands high operating speed of the back-end digital signal processor (DSP). Therefore, how to decrease the operational complexity is a key aspect to be considered in nowadays SR design.When SR is applied in the electronic warfare, the signals to be processed are wide bandwidth ones and the types are various. The receiver works in a passive mode. Therefore, it is necessary to exploit a wide bandwidth receiver with high waveform adaptive ability and perfect augmentability. The channelized receiver based on polyphase filters is a preferable solution scheme. It can realize the wide bandwidth receiving with high intercept probability while the complexity is reduced effectively, which improves the real-time processing ability.According to a specific project, the design of digital filter in wide-band digital down-conversion (DDC) and channelized receiver processing based on polyphase filters are studied under above mentioned background. The main contents are given as follows.Firstly, the basic theories of digital channelized receiver are studied, including theories on multi-rate signal processing, the systematic structure of different software radio receivers, and digital channelized receiver based on polyphase filters.According to the SR theories and project requirements, the system requirements and technological difficulties are analyzed from the system background, specifications, data memories, computational complexity and so on after comprehension of system working situation. System scheme are put forward from viewpoints of algorithm optimization, complexity decreasing and Performance Price Ratio increasing. The sampling rate of ADC, types of main chips and some key points of the hardware design are given.The design of algorithms in MATLAB and FPGA inner programme to realize DDC and channelized receiver processing based on polyphase filters are introduced in detail, which includes the system realization functional analysis and module design. A novel algorithm, clock-selective-computing algorithm suitable for FIR decimation filter is proposed. The consumption of resources is effectively reduced when it is cooperated with symmetry and time-domain multiplexed (TDM).Finally, the testing results of system functions and results analysis are given. The feasibility of the scheme is verified.