| ICNIA general signal processor mostly is the same with general digital process of intermediate frequency and baseband signal in ICNIA system,and has interface function with major control computer. General digital process must be designed with high efficiency and performance by collectivity design idea of ICNIA system.It can dynamic assignable mission and have biggish agility and expansile.With having been read a lot of literature and collected a great deal datum, design project is formed and apparatus are pitched on.Hardware part of the general signal processor is finished:1. The general signal processor is made up of A/D,D/A,FPGA and DSP circuit;2. The general signal processor contains two disposal circuits,in order to deal with two signal.Every disposal circuit contains a A/D and a D/A and a FPGA and a DSP chip;3. Bus separate and drive can be finished both the general signal processor and VME bus.The special interface chip is used to connect LVDS serial bus interface;4. The general signal processor contains a crystal oscillator that the frequency is 40MHz.Two result must be combinated with a CPLD chip and carry to VME bus interface;5. The general signal processor contains two DDS circuits that crotrol sampling frequency of two A/D circuits.ICNIA general signal processor can disposal many signals including HF/U/VHF,IFF,SSR,TACAN/DME/P,MLS,ALT,A BOX AND NEEDLE.TO achieve to collocate and construct and curry and interchange ,signal processor will be designed with disposal of the most complex CNI signal in this design.Primary technology must be resolved :â‘ high speed communications within host computerHigh speed communications within host computer is key technology, we shall adopt FPGA to achieve VME bus following mode interface. High speed communications interface within host computer is 32 bit VME interface that clock speed is 16M. â‘¡the clock of high stability and high speed samplingThe clock of high stability and high speed sampling frequency is key technology in this design too, it must mostly affect capability of the processor. To adapt requirement of changing sampling clock in this system, DDS+DCM technology must be adopted in this project.â‘¢dynamic programme FPGA circuit design.Dynamic programme is a nodus in this design, because the collocate capability of FPGA is biggish and loading scheduling and code format conversion is complex. Dsp is adopted to control FPGA loading circuit. Through the data is exchanged time after time with host computer, FPGA dynamic loading and module EPROM native loading can be achieved.This design can adopt connecting of Dsp expanding bus and VME bus and plenty exert interface function of Dsp expanding bus to finish high intermitting communication of the general signal processor and host computer. DDS+DCM technology must be adopted in this project to get the clock of high stability and high speed sampling frequency. The flexible circuie design must be adopted to finish cosmical FPGA dynamic programme.This design has high flexible and configuring. We consider enough possible arithmetic and its complexity, to provide first-class hardware configuring for more design of software function. This project must have definite advanced place for element choice and combination. |
