An Ultrasound With Variable Center Frequency Digital Bandpass Filter Fpga Design

In recent years, with the integrated chip manufacturing technology development, FPGA obtained the rapid development in the two aspects of the speed and the integration because it has a low power consumption, small size, high integration, high speed, short development cycle, low-cost, re-programming and erasion, and many other advantages, applications continue to expand, more and more electronic systems began to use programmable logic device to achieve digital signal processing.The digital filter takes the important part of the digital signal processing technology, is widely applied in the image processing, the pattern recognition, the pronunciation and the spectrum analysis.The hardware design of the FIR filter mainly uses the special-purpose DSP chip or the FPGA. With the DSP chip which processes based on the software compares, FPGA has prominent merit of the parallel arithmetic structure, may obviously enhance the filter the data turnover rate. FPGA in the FIR filter become a tendency gradually.According to the characteristic of the ultrasonic echo centric frequency ingredient moves along with the detection depth increase , this paper has designed FIR dynamic filter, uses for the automatic selection the diagnosis value frequency components in the ultrasonic echo signal, and filters the strong echo signal by the low frequency primarily in the body surface part and the interferential signal by the high frequency primarily in the depth portion.The design has separately used the three design proposals of serial, direct parallel and the pipelining parallel scheme, and has carried on the comparison to these three performances.The design uses the sapartan3 series apparatus of the Xilinx Corporation, has carried on the synthesis and the simulation through ISE and ModelSim to the entire design. Having carried on the analysis to the result through MATLAB proves the FIR dynamic filter function is correct.