Fpga Implementation Of The Rs Codec

Being an important linear block code in the error control field, the RS code has very strong correction ability, so it is widely used in various modern communication systems as to satisfy the reliability of data transmission channel.This paper mainly discusses the principles and the algebraic configuration method of Reed-Solomon code and its implementation based on FPGA. The performance of the coder and decoder has been shown by simulation, and the correctness has been verified by test. At the end of this paper, the soft decision of RS decoder has been dicussed tentatively.Main work in this paper follows.Firstly, The RS encoder and decoder are realized with FPGA. Secondly, by using the RiBM algorithm, logic units are used less and the speed is also increased. Thirdly, this paper realizes the Galoias multiplier and divider, syndrome circuit and the resolution of the key equation circuit etc via VHDL language. Fourthly, the Chian search progress has been improved in this paper. At last, the chip EP1C40Q324C8 of ALTERA's Cyclone has been used for the implementation of the project.