Fpga-Based Long Code Privacy Amplification Algorithm And Application

With the rapid development of quantum computer technology,the traditional encryption algorithm based on computational complexity is facing great security threats.Based on the basic principles of quantum physics,quantum key distribution(QKD)technology can generate unconditional secure key.Combined with the encryption algorithm of"one-time-pad",the unconditional secure communication is possible.QKD technology can be divided into two categories:discrete variable QKD(DV-QKD)and continuous variable QKD(CV-QKD).The CV-QKD system has a great application prospect because of its low cost and high reliability.In CV-QKD system,the original key is unsafe due to the influence of channel noise and eavesdropper,so it is necessary to remove these influences through post-processing process to obtain unconditional security key.Privacy amplification is a very important step in the post-processing of CV-QKD.It can compress the key and remove the influence of eavesdropper by using the same key of both sides after error correction with the general hash function to ensure the unconditional security of the key.Considering the limited code length effect of privacy amplification in CV-QKD system,the original key length must be improved in order to ensure the security of the final key in long-distance transmission.FPGA is a high integration and high security algorithm implementation platform.The strong parallel computing ability makes it have obvious advantages in the realization of long code privacy amplification algorithm,but limited by the amount of resources,it is difficult to realize large matrix operation on FPGA.Therefore,it is of great significance to study the long code privacy amplification algorithm based on FPGA platform.The main work of this paper is as follows:1.According to the whole process of privacy amplification algorithm,the algorithm is divided into three main steps:matrix construction,data extraction and privacy amplification.Matrix construction needs to solve the problem of large amount of stored matrix data when the original code length is 100MB.In this paper,linear feedback shift register(LFSR)is used to generate data that meet the Toeplitz matrix construction conditions,and the storage resources are greatly reduced.Data extraction is to extract the matrix data according to the address information provided by the private key amplification module,in which the initial matrix with size of 1M×100M is divided into two blocks,the first block is divided into the first-order submatrix of 1M×1M,this is determine the size of RAM to store LFSR results;the second block is to divide the first-order submatrix into the second-order submatrix with the size of 512×512.The XOR algorithm is used to accelerate the matrix multiplication in the privacy amplification operation,which reduces the complexity of the algorithm to O(n).2.Combined with the strong parallel computing ability of FPGA to improve the processing speed of the algorithm,and the method of module reuse is used to reduce the resource consumption of FPGA.Finally,this paper uses Verilog HDL language in FPGA platform to realize the original key processing under the condition of 100MB code length.The simulation and hardware test of each sub module and the main module are carried out to ensure the normal timing and function.Finally,when the compression ratio is 0.01,the final data processing speed is 33 Mbps,and the overall resource consumption of the algorithm is only about 1/4 of the selected FPGA.