If Digital Receiver Design

Around the thesis of All Digital Broadband IF signal receiver, the design focuses on the hardware platform of parallel A/D sampling, IF signal DDC and the baseband signal processing. In order to realize the SDR and to enhance the performance of the system, some algorithms are adopted such as Cordic algorithmn in the frequency mixing and the phase derivation detection of the QPSK signal. And the paper also works on the cascade of HB and FIR filters coefficient design. Finally, in the baseband, we analyze and choose an approach for demodulation, which requires the bit timing firstly and then the carrier phase recovery.The whole data processing flow and the main techniques used in the design are as follows: analog IF modulated signal firstly sampled by two parallel ADC of the receiver in 150 MHz sampling rate separately, then through the DDC module in the FPGA, the I, Q channels signals are separated and the rate of the processing data is further lowered to the baseband signal rate; then we demodulate them in the DSP. And the end of the paper, the QPSK signal, which has a rate of 390.625Kbps, a timing derivation of 1% of the code period and10dB SNR, is successfully demodulated in the simulation way and we can check the algorithms and the software design through the demodulation constellation in the MATLAB and CCS.