Aes Encryption Mechanism In The Ipsec Protocol And Its Hardware Implementation

Along with the rapid development of the Internet and its applications, Internet has already transited to a commercial behavior from its initial purpose as academic communications. This transition requires the higher network security, so that maintaining the security of the high speed network attracts great attention. Under the condition of well keeping the network security, in order to pursue the higher network speed, the high speed hardware encoding equipment will be required. On the other hand, IPSec protocol has been widely used in fire wall and security gateway, which however increased the load of the network gateway and results in a bottleneck of the achieving the Gigabit network. Regarding the current situations mentioned above, this thesis studied the designing technique and realization of AES algorithm based on high performance of FPGA, which was an important part of IPSec protocol.AES is new standard for data encryption and decryption. There is a lot of relevant research so far, but most researches are about non-feedback mode, and only support 128bits key. In this thesis, a compact and reliable hardware AES encryption and decryption system is designed, which supports all three key length of 128, 192, 256 bits, supports both ECB mode and CBC mode. The two key rounds of AES algorithm, SubBytes and MixColumns, are optimized to realise substructure sharing. The design comes true by fully validation and it reduces the number of gates by 18%.