Low Phase Noise Cmos Vco, Dual Control Loop To Achieve

Because of the rapid development of the wireless communication technology, the design and research of the integrated circuits in the related field has gained more and more attention in recent years, System on Chip (SoC) has become the main focus of the wireless communication areas.So, with the growing interest in high-integration implementations there has been an increasing demand for fully-monolithic, on-chip VCO and synthesizer designs. Delay cell based VCOs (ring-oscillators) have been used successfully in many applications, but thermal-noise induced timing jitter and phase noise has limited their applicability to some systems. Of particular interest are frequency synthesizers, used in wireless communications transceivers, which have stringent requirements on oscillator phase noise but stand to benefit from a highly integrated solution.In this thesis the fundamental theory of ring oscillator VCOs and Practice circuit design are investigated. The effects of thermal noise in transistors on timing jitter and phase noise of source coupled differential resistively-loaded CMOS delay cell is explored. The relationship between delay element design parameters and the thermal noise-induced jitter are analyzed and implicate this analysis for the design of low-timing-jitter and low-phase-noise VCOs. In full integrated PLLs, the VCOs output frequency should be tunble over a wide range of frequencies, for all the process variation and work conditions. This range realized by making the VCOs gain Kvco large has the unwanted effect of increasing the phase noise at the output of VCO, and hence of the PLL as well.So, by using the two control loops to make a low VCO gain. In addition, the center frequency of a VCO can vary with changes in the power supply, temperature. Designing a VCO which is resistant to drift and has an ample tuning range to cover these variations are very important, this will be implement with some bias circuits. At last, this design has been tap out with JAZZ 0.35μm BiCMOS process.