Sigma-delta Adc Decimation Filter Realization

The research and design of decimation filter in sigma-delta ADC is introduced in the paper.Sigma-delta ADC is widely used in consumer digital audio receivers, digital audio recorders, including portables CD-R(Compact Disc Recordable), DCC(Digital Content Creation), MD (MiniDisc), and DAT(Digital Audio Tape), multimedia and consumer electronics equipment, sampling music synthesizers. The research on the audio system ADC chip has great practical significance.Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at Nyquist rate. This paper presents an efficient design and implementation of a digital decimation filter with a downsampling ratio of 256, which can be used in third order(2-l cascaded) sigma-delta modulator, and input word length is 2 bits. The proposed decimation filter consists of Cascaded-Integrated-Comb (CIC) filter, compensation lowpass filter and narrow transition-band Finite Impulse Response (FIR) filter using Canonic Signed Digit (CSD) number system. Multi-stage multi-rate signal processing is used to implement compensation lowpass and half-band filters.The circuit's parameters are 1.8 V digital part power supply,98 dB (Typ) dynamic range, 96 dB (Typ) S/(THD + N),18bit ENOB ,0.006 dB decimation filter pass-band ripple, 110dB stop band attenuation, four-stage, linear-phase decimator, 256 downsampling ratio.The whole design starts from Matlab system simulation,Verilog HDL RTL coding,Modesim SE RTL netlist simulation and gate level netlist simulation,Synopsys Design Compiler synthesis,Encounter place and route,Calibre DRC and LVS.The whole filter is verified using FPGA and fabricaded in the process of 0.18um CMOS mixed-signal technology. The result of the chip testing proved the success of the chip.