Based On Turbo Code, The Fpga Hardware Design And Performance Analysis

With the development of the communication techniques and the higher request of transmission information from military and public, the Error-Correcting Codes techniques can not only be researched theoretically, they must be taken into the actual application. Now they have already become key techniques in the most of the communication system.At first, this text introduces the encoding system structure, focuses on the recursive system convolution code and interleaver, which are important in Turbo encoder. Then, the structure of decoder is introduced. Later, the iteration decoding and a new algorithm that takes the Exterior Information and Cross Entropy as the iteration stopping rule, are also studied. The simulation shows it can get the expected results.Then, software simulation model with the decoder, encoder and channel, is constructed. With specific parameters, simulation is performed and we get the simulation results. Based on the software simulation results, we design the hardware circuit of Turbo decoder and use the FPGA to the core of the hardware circuit. Because it requires larger memory to use storing iteration information, we bring on using the exterior memory to store it. So this way can save the half of the hardware resource, and enhance the resource using rate much better.At last, analyzing the performance of hardware circuit design, farther we compute and analyze the guide line that is important attentive and checked in practice, comparing to software simulation. The guide line of the decoding delay and resource both are almost consistent, and meet the communication requests, so validate the performance of the circuit design is reasonable and correct.