Smt Structure Of The "dragon R2 Microprocessor-based Study

The work in this dissertation is part of National project entitled "Application Specified High Performance Microprocessor (Longtium R2)", the purpose of the project is to design embedded 32 bits microprocessor, whose instruction set is compatible with PowerPC, by studying RISC architecture and exploring design methodology.The instruction set and the interface timing of the embedded 32-bit microprocessor "Longtium R2" is compatible with Motorola's PowerPC 750 microprocessor. The architecture is full copyrights, using the Top-Down design methodology. The ASIC chip had been successfully taped out. The author is responsible for the design and implementation of the processor's fixed-point executing unit. Based on that, the author perform in-depth research on the fetching strategy and branch prediction of the SMT architecture.This dissertationr mainly studies for the following:1. By studying the PowerPC architecture, design the "Longtium R2" fix point pipeline, which has 6 stages. Use the issue queue and completion queue to guarantee the program order.2. Sort the exception of "Longtium R2", complete the precise exception processing and dependency processing of the "Longtium R2" pipeline.3. Complete the front-end architecture of the "Longtium R2" fix point pipeline, include BPU and instruction fetching unit. The BPU use static and dynamic branch prediction algorithm optionally, meanwhile we use the BTIC to accelerate the speed of branch processing.4. Analyze the limitations of the "Longtium R2" superscalar processor, combining how to further improve the current "Longtium R2" processor, propose "Longtium R2" SMT pipeline architecture and finally run the architecture-level simulation by SMTSIM simulator.5. Focus on researching of the fetch strategy and the branch prediction of SMT architecture, design "Longtium R2" SMT processor's instruction fetching controller and run some necessary simulation by SMTSIM simulator.