Based On The Altivec Vector Processing Unit Alu Design

Based on a Research Projects undertook by the microelectronics aviation center of Northwestern Polytechnical University, made an in-depth study on the expansion of the multimedia functions in series of "Longtium" microprocessors. Using a top-down design method with the hardware description language Verilog, design independently and make an implementation of VSIU (vector simple integer unit) and VCIU (vector complex integer unit) , which were parts of the vector process unit's VALU (Vector-ALU) based on the AltiVec technology. Then make verification and synthesis.The research work of this dissertation mainly includes:1. Study deeply the AltiVec technology how to enhance the multimedia functions based on the PowerPC architecture, including their instruction set, operand conventions, addressing modes, memory management and exceptions. Under the characteristics of AltiVec instructions and operands, using the multiplex design, have reduced the complexity of the design and verification, data bandwidth from 128-bit down to 32-bit.2. Systematically analyze the simple vector integer arithmetic instructions, division the VSIU according to their functional, have designed the vector adder unit, the vector rotation / shift unit, the Vector Floating-point comparison unit, the vector logic unit four sub-modules. Vector Adder modular design using a variety of design methods. The results showed that the adder designed by top-down method is the suit option. It can save circuit area under the condition that insure of the timing of the unit. Vector rotation / shift use a variety of design methods, the method based on byte shift is the best one, it can greatly increases the efficiency of circuit and save the circuit area as the same time. Compared to the simplest design method, the method based on byte shift reduces the circuit area of 67%.3. Systematically analyze the complex vector integer arithmetic instructions, design the multiplication and addition module of VCIU according to their functional. According to the manual, as well as all parts of the module delay, design the Multiply-Add, Multiply-Sum, Sum-Across-Partial pipelines. Under the further analysis of the pipelines' characteristics, make an Integration of those pipelines, don't impact the performance and save the circuit area of 21.4%.