Sige Hcmos The Ic Key Technology Research

As the silicon-based technology has developed to its limit, it is urgent to search for a procedure that can maintain the development of nowadays technology. SiGe material can be a candidate. Using a strained Si layer as a channel in CMOSFET may increase the mobility of carriers and thus enhance the device's performance considerably such as transconductance and cutoff frequency. It is difficult to obtain SiGe HCMOS because of its special technics.In this thesis, the optimized design and critical fabrication technics have been analyzed. SiGe HCMOSs have been fabricated successfully.The main results are as follows:1. Through theoretical analysis and computer aided simulation, optimized design process of strained Si channel Si/SiGe heterostructure devices are given, including the thickness of gate dioxide and each epitaxy layer, Ge content, the doping of each epiatxy layer. In light of them, matching PMOSFET and NMOSFET with strained si channel were designed.2.The epitaxy layers including LT(Low Temperature) Si grow technicsare discussed. RMS(Root-Mean-Square) of sample surface is 1.02nm in a scanning range of 10×10μm2 and degree of relaxation of SiGe layer is 85 %.3.To avoid the high temperature process in SiGe CMOS technics, appropriate implantation energy and dose and RTP (rapid thermal anneal) are introduced into the the fabrication of SiGe CMOS double-well and source.4.Investigation are made into preparations of thin gate-oxides for strained Si channel MOSFET's using PECVD at 300℃and low-temperature (700– 800℃) thermal oxidation, respectively.