Jpeg Decoding Algorithm In The Multi-cpu Embedded System Implementation And Performance Optimization

The JPEG compression algorithm takes one kind of highly effective static state image data compression algorithm. The widespread application of JPEG in multitudinous inserted in the type multimedia product the image data code and the decoding speed has already become a most important aspect which the restriction product performance enhanced. In the embed environment with single CPU, JPEG arranged the decoding speed already nearly to the limit and it is difficult to have the promotion space. Recently as the representative of embed multi-processor system, FUJITSU FR1000's appearance provide the possibility for hardly promoting the performance of multimedia product. Therefore, this topic take the JPEG decoding algorithm working in the development environment of multi-processor embed system as the research object.This dissertation analyzed the multi-processor embed system and the JPEG decoding algorithm and principal characteristic and the application prospect of themselves. We discussed that how to optimize the JPEG decoding algorithm in the embed system development environment and how to utilize the given hardware resources extremely. In this dissertation, we explain the JPEG decoding algorithm in details and analyze the feasibility of revising original algorithm to fit for the multi-processor hardware according to its characteristics and finally realize it. This dissertation mainly focuses on the JPEG decoding algorithm optimization and its realization in the embed system, shows the core of software realization. On the other hand, it briefly introduced VLIW (Very Long Instruction Word) the ultra long set of instructions construction and some concepts of insert-assembly and hardware.