Optimized VLIW Compile Technologies For High Density Computing On FT64 Stream Processor

The stream architecture is one emerging high performance architecture in recent years. FT64,as the first 64-bit stream processor designed and implemented by ourselves in our country, in order to expose the parallelism in programs,it adopts the SIMD and VLIW execution model in its kernel-level,and in order to support the demand of register capacity and rate by large-scale function unit array,it adopts distributed register file structure in the cluster.The VLIW technology is propitious for the chip to upgrade the frequency and to reduce the power consumption,mean while,it needs the compiler to meet more requirements.When the application expanded,as the demand of register by application augments rapidly,the capacity of single register file in the distributed register file becomes one of the bottlenecks during programming and compiling.This paper studies the VLIW compile technology in the stream processor,and our goal is to offer a high efficient compiler for the FT64 stream processor,and to offer compiling support for the high performance execution of the program.Based on the source code of ISCD compiler and the existing research,and according to the background of application and the demand of project practice,this paper implements the kernel-level compiler for the FT64 stream processor.After researching the correlative background,the implementation of the compiler focuses on the choice of different strategies and the management of the bottlenecks and the implementation of project.The communication scheduling ensures that when aiming at the shared interconnect architecture,the VLIW scheduling can still sustain high efficiency.In the condition of not reducing the program performance,the load schedule strategy makes the register allocation successful,avoiding the performance loss caused by the failure of register allocation.The operation combining technology combines the multiplication operation and addition operation automatically, improving the efficiency of the compiler.The compiler designed and implemented by this paper has been used in the system running, and gets good effect.This paper also tests and analyses the performance of the compiler on the FT64 stream processor.The result shows that after taking the optimized methods,the compiler can identify the parallelism in the program,getting prospective purpose.