Strained-soi Mos Device Design And Optimization

Strained-SOI MOSFET, which appears recently, takes both the advantages of SOI (Silicon on insulator) and SiGe (Silicon Germanium). It has shown advantages over bulk sample in enhanced carriers mobility, as well as higher transconductance, stronger drive capability and reduced parasitic capacitances. These properties make it a promising candidate for improving the performance of microelectronics devices. However, study on this subject is mainly focus on material fabrication technology currently. Physics device model, component structure design and fabrication technology are discussed based on the thorough analysis of strained silicon and SOI physics mechanism. The detail contents are as follows.The analytical threshold voltage model, drain current model and transconductance model are derived from Poisson's equation for the fully depleted strained SOI MOSFET. Influences of the parameters on device performance such as thickness of Strained Si, Ge content, channel doping and thickness of buried oxide are discussed based on given models. The models could be very helpful for device design.After structure design aimed to high transconductance, parameters of device structure are modified in detail. The simulation results of SOI NMOS with strained Si channel show great enhancements in drain current, effective mobility (74%) and transconductance (50%) beyond conventional bulk Si SOI NMOSFET.The Strained-SOI NMOSFET fabrication process is proposed with LT-Si (low temperature-Si) technology for relaxed SiGe layer and SIMOX technology for buried oxide. Problems about fabrication of SiGe-OI substrate, low-temperature gate oxidation and source/drain ion implantation are discussed after considering technology level and reported articles. The key points in fabrication process are proposed and theoretically analyzed. At last, device layout design is discussed in detail.