Channelized Digital Receiver Hardware Research

With the fast development of modern electronic technology, electronic reconnaissance equipment is facing the challenges from the more and more complicated electromagnetic environment. The wide band, the digitization, multi-purpose, the software already became the tendency which the electronic reconnaissance equipment develops. The general electronic warfare reconnaissance receiver, at the same time the multi-signal processing ability is weak, it only can do single signal processing per time. To process more signals, common receivers use pipeline and time-sharing method which is totally unsuitable for the extremely complicated electromagnetic environment in the modern war. Digital channelized receiver is good at real-time signal processing, especially at improving ability of whole probability capturing as well as resolving the problem of channels'in-equilibrium of analog channelized receiver.Consulting relevant reference and related theories in software radio, this thesis is working on technologies of digital channelized receivers, including the theories on A/D sampling, digital down converter, multi-velocity signal processing, polyphase filter and uniform DFT filter bank.According to the requirements on the system, this thesis accomplishes the design of the system's hardware platform to realize channelization while evaluating the A/D sampling circuit and validating the functions of the hardware platform. In the design process of hardware I studied in depth the A/D sampling circuit performance indicators and related test methods, while providing guidelines on design of the high-speed PCB circuit.At last, this thesis realizes digital down converter based on FPGA, and the whole designing process includes algorithm simulation, VHDL description, FPGA simulation and real system test. Information on IP core and EDA software offered by the chip manufactures is fully used to complete the system design, simulation and test.