Hdtv Test Pattern Signal And Fpga System

High Definition Television (HDTV) is a new technology which is developed and syncretized by high technological production such as Information Theory, Digital Signal Processing, Computer Technology, SLSI (Super Large Scale Integration), Communication Technology and so on. Along with Digital HDTV's springing up, testing and assessment of HDTV system and equipments'running quality become a hotspot of television industry. Viewable test pattern signal provides an intuitionistic and convenient evaluating method, therefore, HDTV test pattern signal generating system become a hot research of world today. This system plays an indispensable role in HDTV program's making and playing system, scientific research, production and maintenance department.The thesis researchs the basic theory of digital HDTV test pattern signal generating system and its realization based on SOC (System On Chip). The system generates 18 kinds of worldwide used HDTV test pattern signals supported by SMPTE 274M standard, and also provides YPbPr, RGB video outputs both in digit and analog and the output interfaces of ITU-R BT.1120-2/ GY/T157-2000 Studio HDTV Digital Video Signal Interface Standard.The thesis firstly summarizes the current research of HDTV test pattern signal, and introduces the HDTV technology, HDTV signal design reference standards, such as SMPTE international standards and Chinese standards for HDTV digital video signal interface of studio. The thesis then introduces top-to-bottom schemes, which discuss the functional design of HDTV test pattern signal generator according to the tasks and platform of the system, and develops the function of subsystems.The thesis analyses the theory and mathematic model of HDTV test signal, and studies the signal generating scheme called Single-FPGA and Multi-PROM, and describes in detail its key modules such as configuration connecting, PROM routing, control and switch timing design and so on. The Single-FPGA and Multi-PROM scheme increases the number of PROM to reduce the degree of FPGA demanded, thus...