Simulink Model Into Eda Tools For The Design, Rtl Description

The system simulation environment SIMULINK of MATLAB is widely used in current FPGA design. After designing and simulating the system, the system engineer will ask the IC engineer to realize the design on certain FPGA chips. During the procedure of realization, Hardware Describe Language (HDL) is commonly used. The system engineer and IC engineer, co-operating in the whole design process of the way introduced above, could work effectively in each of their own fields. Nowadays so many FPGA vendors have developed various EDA tools to support this design flow, which make this scheme widely accepted.But, for the part of control logic design, there is no efficient enough tool to build a bridge between system engineer and IC engineer.This article gives off an idea to parse and convert the Stateflow chart in SIMULINK through analyzing the traditional way of FPGA design. That is utilizing the API provided by MATLAB itself to complete the conversion from Stateflow chart to Verilog HDL description. If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up. The FPGA design flow, the characteristics of Stateflow chart and the design process of the convert tool will be illustrated in the article for detail.In addition, another analysis tool will be illustrated in the article detailedly. This tool could analyze the connection relationship between the submodels of the system designed with SIMULINK and give out a Verilog HDL description of the netlist.