TCP-stream Reassembly And Consignation In ASIC

The band width of network has reached Gbit, with the development of fiber network, and it will reach 10 Gbit even more. It has been proved by a lot of facts that the bottle-neck from end to end in high-speed network is the termination of TCP-stream. Terminal CPU is a generic component, whose efficiency of process TCP protocol is low. In order that the end-user can take advantage of the vastitude band resource, the process of TCP-stream must be offloaded from host-CPU to ASIC. This paper introduces the fore-design of this ASIC.At first, I frame the architecture of the processor, and plot out function module according to the protocol's characteristic. It makes up of input-fsm module, register-file module, link-supervise module and three connection module, and each connection sub-module contain six module, such as macro-fsm module, data-slip module, the controller of memory access module, packet filter module, generation-point module and memory.Secondly, contrive each module in Verilog-HDL, and validate the RTL-processor by ADLC's emulator Active-HDL 6.1Thirdly, synthesize the design by Synopsys's Design Compiler, convert the RTL-module to gate-level netlist. Then distill the Verilog file and time-delay file from this netlist by DC, and validate the gate-level netlist in Mentor Graphics' emulator ModelSimSE PLUS 5.8.At last, validate all path's scheduling in Synopsys's static scheduling analysis tool Prime Time, and the result indicate that processor's clock frequency may attain 100MHZ. the ability of process TCP-stream achieves the 3.2Gbit network's wire-speed.The processor offloads the task accomplished by software from host CPU to ASIC, and separates the application and network, and makes the end-user make full use of the abundance band. The development of this processor provide stability base for our country to develop the intellect self-determination high layer chip.