Fpga-based High-speed Dedicated Digital Downconverter

The coming of Software Defined Radio (SDR) redefines the way to implement receivers. With the theory getting more matured and completed, SDR technology has been widely used in cellular communication system as well as other civil and military wireless communication systems. Accordingly, Digital-Down Convert (DDC), one of the core technologies used by SDR receivers, is also getting more and more extensive application. Based on the research project, High Speed Dedicated DDC Based on FPGA, and after an in-depth study of the rationale and technologies used by abroad mainstream DDC products as well as the characteristics of FPGA and possible application areas, this paper improves the maximum processing speed and processing bandwidth of DDC greatly by improving the system architecture of traditional DDC and implementing some of the modules in unconventional ways. The two important criteria, Processing Speed and Processing Bandwidth, outgo most of the abroad mainstream DDC products, thus achieving the aim to be High Speed and Dedicate. The design also pays much attention to the device's functionality and assures the generality of product. The design uses Stratix series FPGA and is validated on Altera's Stratix S80 DSP Develop Evaluation Board and a customized DDC dedicated development board. Functional tests indicate the success of this design. After introducing basic theory and architecture of DDC and summarizing various key algorithms such as CORDIC, CIC, HB, DA, Resample, etc, that are used by different function unit, this paper proposes an architecture based on FPGA implementation and corresponding performance analysis. By studying the constraints among the modules at DDC system level, balanced modules'parameters and maximized overall performance are achieved by choosing rational configuration optimize DDC architecture. At the end of this paper, waves and spectra generated by FPGA DDC during tests are given and test results are analyzed.