Eight Microprocessor Ip. Nuclear Design And Research

With the development of electronic thchnology, IP core become more and more importment in the field of SoC.In order to find out the control factors that limit the performance of the typical 8-bit MCU, a systematical analysis of MCS-51 has been carried out in this thesis. It has been found that the major limitations of typical 8-bit MCU are the ALU structure based on accumulator ,the clock system design and the CISC architecture adopted in MCS-51 design. Then a Top-Down design of 8-bit RISC micro-controller is presented to overcome the limitations of the MCS-51. The core is based on Harvard architecture with 16-bit instruction length and 8-bit data length. The performance of MCU has been improved greatly by introducing signal-cycle instructions, adopt the multiply and divide module independently, setting multiple high-speed working registers and replacing micro-program with direct logic block etc.To keep the MCU core reusable and transplantable, the whole MCU core has been coded for synthesis in VHDL. It is shown from FPGA verification and computer simulation that the MCU core's maximum clock frequency and instruction efficiency are three times higher than those of typical of MCS-51 chips.