Vlsi Design Process Of Validation Technology And Practice

As the scale of chips increase exponentially, verification trails far from design, and verification is becoming the bottleneck of designing and producing much greater and more complex chips. In order to solve the problem, the field of verification has been developed greatly. This paper points that the activity of chip's verification is no longer hardware testing, but a hardware testing with basic rules of software testing. Directed by this idea, more requires are promoted of testbenches than efficiency and functionality. Expansibility, code coverage and regression test also possesses great importance.Higher goals demand for more powerful tools. Synopsys's Vera is one of the most modern languages designed specially for making testbenches. Main characteristics include object-oriented language core, interfaces between Vera core and HDL implemented by interface definition and port variables, complex concurrency control implemented by programming construction (fork/join) and data structures (event, mailbox and semaphore, etc). All these help Vera successfully model hardware properties.In this paper, we take the verification experiences of video post-process chip as example, analyze the testing course of video display module and algorithm module, emphasize different sides of between module level and system level, and summarize the gains and fails of the chip's verification.Static verification also provides great help to dynamic verification mentioned above. And formal verification is one form of static verification. This paper analyses patial sequential theory of formal verification, states the principle of modeling complex systems. After evaluating Synopsys's Formality, the paper construes the flow and practical experiences in Video Post-process Chip, and comes to the conclusion that static verification really works.This paper is composed of four parts. The first part discusses about the strategy of verification; the second one analyzes Vera; the third focuses on the anatomy of verification work in Video Post-process Chip Version 2, the last one probes into the formal verification theory, and summarizes the flow according to practical experiences.